| 摘要 |
A semiconductor memory device is provided to accurately analyze the cause of an access fail, by controlling only the enabling time and enabling width of an address-strobe signal by applying a test signal. An internal clock generation unit(100) generates an internal clock by receiving an external clock. A test address-strobe signal generation unit(200) generates an address-strobe signal in response to the internal clock, and controls the enabling time and pulse width of the address-strobe signal according to a test signal. An internal address generation unit(300) outputs an internal address by receiving an external address in response to the address-strobe signal.
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