| 摘要 |
A latency control circuit of a semiconductor memory device is provided to improve operation performance by changing latency according to refresh during a burst read operation in a synchronous pseudo SRAM. A precharge part(10) outputs a precharge reset signal to extend latency during a burst read period where a refresh operation is performed according to a refresh signal and a normal active signal. A refresh period detection part(20) detects a refresh period according to the precharge reset signal and a latency setting signal including the latency extension information, and then enables a latency extension signal during the burst read period, and disables the latency extension signal when the precharge reset signal is enabled. A latency decoder(30) outputs a latency pre-signal including latency information fixed by decoding an external address. A latency control part(40) outputs a fixed latency signal according to the latency pre-signal during a period where the refresh operation is not performed, and extends the cycle of the latency signal according to the latency extension signal during a period where the refresh operation is performed.
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