| 摘要 |
A wafer test apparatus and a method using the same are provided to modify easily a test program and to reduce a test time by using a BIST(Built In Self Test) logic. A wafer test apparatus includes a probe station. The probe station includes a probe card. The probe card includes a plurality of BIST logics. The number of BIST logics formed in the probe card is in a range of 8 to 12. The 8 to 12 BIST logics are used for testing sequentially a plurality of chips, so that the size of the wafer test apparatus itself is reduced and a wafer test time is remarkably decreased.
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