| 摘要 |
An asynchronous gray-code counter is provided to increase the circuit size, as removing a glitch phenomenon in the asynchronous counter by adding a minimum number of flip flops. An Nth flip flop(DF11) outputs a first output signal according to a clock signal. A (N+1)th flip flop(DF12) receives the first output signal of the Nth flip flop as an input signal, and then outputs an output signal according to the clock signal, and supplies an input signal of the Nth flip flop at the same time. A (N+2)th flip flop(DF13) receives the output signal of the (N+1)th flip flop as a clock signal and outputs a second output signal having a half period of the first output signal, and feeds back an input signal at the same time. A (N+3)th flip flop(DF14) receives an inverted output signal of the (N+1)th flip flop as a clock signal, and outputs a third output signal having a half period of the second output signal. A (N+4)th flip flop(DF15) receives the third output signal of the (N+3)th flip flop as an input signal, and outputs a fourth output signal having a half period of the third output signal according to the same clock signal as the (N+3)th flip flop.
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