发明名称 |
Information processing apparatus with central processing unit and main memory having power saving mode, and power saving controlling method |
摘要 |
A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.
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申请公布号 |
US2007006002(A1) |
申请公布日期 |
2007.01.04 |
申请号 |
US20060514923 |
申请日期 |
2006.09.05 |
申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
SHIRAGA SHINJI;MINABE OKI |
分类号 |
G06F1/00;G06F1/32;G06F12/00;G06F13/42 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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