发明名称 SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH A SUPERLATTICE THEREBETWEEN AND ASSOCIATED METHODS
摘要 A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularl y, at least some of the STI regions may include divots therein. The semiconduct or device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.
申请公布号 CA2612213(A1) 申请公布日期 2007.01.04
申请号 CA20062612213 申请日期 2006.06.20
申请人 MEARS TECHNOLOGIES, INC. 发明人 RAO, KALIPATNAM VIVEK
分类号 H01L21/8238;H01L21/762 主分类号 H01L21/8238
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