发明名称 Wide-port context cache apparatus, systems, and methods
摘要 Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for exclusive use by a selected lane in a multi-lane serial-attached small computer system interface (SAS) hardware protocol engine while the selected lane processes a selected one of the frames.
申请公布号 US2007005888(A1) 申请公布日期 2007.01.04
申请号 US20050171960 申请日期 2005.06.29
申请人 INTEL CORPORATION 发明人 HALLECK WILLIAM;SETO PAK-LUNG;LAU VICTOR
分类号 G06F12/00;G06F12/14 主分类号 G06F12/00
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