| 摘要 |
An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.
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