| 摘要 |
A system and method of reducing the pulse width differential in a phase frequency detector (PFD) is provided. In the first embodiment (fig. 3), a PFD is construed using a plurality of flip-flops (310,320,330,340,350,360) and a plurality of logic gates (370,380,372,374,376,378). A set of flip-flops (310,340) are adapted to receive a plurality of inputs and a plurality of clocks and to latch the inputs at transitions in the clocks. A fist logic gate (380) is then used to reset the first set of flip-flops and a second set of flip-flops if the inputs are latched (i.e. the clocks are active. If an input is not latched (i.e., a clock is inactive), then the fist and second set of flip-flops are not reset, and the outputs of the PFD are forced to zero. Once the inactive clocks are reactivated, a third set of flip-flops (330,360) is used to hold the first set of flip-flops in a reset state for a period of time (e.g., half a clock cycle). Once the period of time elapses, the first set of flip-flops(310,340) are released from its reset state, and normal operation is resumed. In a second embodiment (fig. 6), a signal (or alarm) is provided to indicate that a clock has become active. In a third embodiment, at leas one logic gate is used to force the first set of flip-flops into a reset state. This can be done, for example, when changing a clocks source or switching clocks.
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