| 摘要 |
A delay locked loop circuit is provided to prevent clock synchronization error regardless of the phase change of a feedback clock applied to a phase detection part during an initial operation of the delay locked loop circuit, by controlling the selection of an external clock and an inverted external clock and the setting of delay period of the clock independently with each other. A clock receiver part(200) outputs an external clock and an inversion clock of the external clock and a reference clock. A MUX(210) receives the external clock and the inversion clock, and outputs one of the clocks selectively. A first delay part(220) delays an output signal of the MUX by a first delay period. A clock driver(240) generates an internal clock by receiving a signal from the first delay part. A second delay part(260) outputs a feedback clock by delaying a signal from the clock driver by a second delay period. A phase detection part(270) compares a phase of the reference clock from the clock receiver part with a phase of the feedback clock from the second delay part, and outputs a first phase control signal to control a selection operation of the MUX and a second phase control signal to control a delay operation of the first delay part.
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