发明名称 METHOD FOR MANUFACTURING INTER METAL DIELECTRIC LAYER OF SEMICONDUCTOR DEVICE
摘要 A method for manufacturing an interlayer dielectric of a multi-layer metal wire of a semiconductor apparatus is provided to increase yield of an interlayer dielectric of the multi-layer metal wire by preventing crack generation of an inter-metal interlayer dielectric using an SOG(Silicon On Glass). A first inter-metal interlayer dielectric(108) is formed on an upper portion of a lower structure(100) of a semiconductor substrate having a lower metal wire(102). A contact electrode(110) is formed to be connected to the lower metal wire through the first inter-metal interlayer dielectric. An upper metal wire(112) is formed on an upper portion of the first inter-metal interlayer dielectric to be connected to the contact electrode. An SOG is firstly applied on upper portions of the inter-metal interlayer dielectric and the upper metal wire with a first thickness, and annealing is performed on them to form a second inter-metal interlayer dielectric(114). The SOG is secondly applied on an upper portion of the second inter-metal interlayer dielectric with a second thickness, and an annealing process is performed on it to form a third inter-metal interlayer dielectric.
申请公布号 KR20070001744(A) 申请公布日期 2007.01.04
申请号 KR20050057377 申请日期 2005.06.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE, WON MO
分类号 H01L21/31 主分类号 H01L21/31
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