发明名称 WIDE-PORT CONTEXT CACHE APPARATUS, SYSTEMS, AND METHODS
摘要 Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for exclusive use by a selected lane in a multi-lane serial-attached small computer system interface (SAS) hardware protocol engine while the selected lane processes a selected one of the frames.
申请公布号 WO2007002804(A2) 申请公布日期 2007.01.04
申请号 WO2006US25304 申请日期 2006.06.29
申请人 INTEL CORPORATION;HALLECK, WILLIAM;SETO, PAK-LUNG;LAU, VICTOR 发明人 HALLECK, WILLIAM;SETO, PAK-LUNG;LAU, VICTOR
分类号 G06F3/06 主分类号 G06F3/06
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