INTEGRATED SRAM CACHE FOR A MEMORY MODULE AND METHOD THEREFOR

摘要

A memory module having at least one random access memory device and a memory bus on a substrate. The memory module further comprises an SRAM cache interfaced with the random access memory device through an ASIC associated with the SRAM cache and operable as a prefetch controller for the SRAM cache. The ASIC and SRAM cache cooperate to enable data to be prefetched and cached during idle cycles of the memory device, thereby increasing the overall operating speed of the memory circuit by minimizing latencies should the prefetched data be requested. The ASIC can be programmed to prefetch not only data from the originally accessed row during a read operation, but also to speculatively prefetch data from logically coherent rows in order to anticipate and counteract a page miss and the associated latencies based on the locality of data.