发明名称 BULK RESISTANCE CONTROL TECHNIQUE
摘要 <p>The present invention provides a MOS transistor device for providing ESD protection comprising at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one isolation gate formed in at least one of the interleaved fingers. The device can further comprises a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.</p>
申请公布号 WO2007001860(A2) 申请公布日期 2007.01.04
申请号 WO2006US23147 申请日期 2006.06.14
申请人 SARNOFF EUROPE BVBA;SARNOFF CORPORATION;VAN CAMP, BENJAMIN;VERMONT, GERD 发明人 VAN CAMP, BENJAMIN;VERMONT, GERD
分类号 H01L29/76 主分类号 H01L29/76
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