| 摘要 |
A semiconductor memory and a burn-in test method thereof are provided to reduce a burn-in test time by optimizing a voltage applying pattern to a bit line. According to a burn-in test method of a semiconductor memory, high and low voltage levels are applied to each bit line of bit line pairs during a first step. The opposite voltage level to the previous step is applied to a bit line pair of a twist structure while the same voltage level as the first step is applied to a bit line pair of a parallel structure, during a second step. The opposite voltage level to the first step is applied to the bit line of each bit line pair, during a third step. The opposite voltage level to the third step is applied to the bit line pair of the twist structure while the same voltage level as the third step is applied to the bit line pair of the parallel structure, during a fourth step. The opposite voltage levels are applied to adjacent bit line pair, respectively, while one of high and low voltage levels is applied to the bit line pairs in common, during a fifth step. The opposite voltage level to the fifth step is applied during a sixth step. The voltage applying time to the bit line pair of the six steps is equal.
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