发明名称 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion
摘要 A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third memory cell transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.
申请公布号 US7158398(B2) 申请公布日期 2007.01.02
申请号 US20050052792 申请日期 2005.02.09
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIMIZU AKIRA;SHIROTA RIICHIRO;ARAI FUMITAKA
分类号 G11C5/06;G11C16/04;G11C11/34;G11C16/02;G11C16/06;G11C16/08;H01L21/8247;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C5/06
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