| 摘要 |
A memory ( 100 ) includes first ( 116 ) and second ( 118 ) sense amplifiers, a first logic gate ( 120 ), a first three-state driver ( 130 ), and a latch ( 180 ). The first sense amplifier ( 116 ) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier ( 118 ) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three-state driver ( 130 ) has a data input terminal coupled to the output terminal of the first logic gate ( 120 ), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch ( 180 ) has an input/output terminal coupled to the global data line ( 170 ).
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