| 摘要 |
A semiconductor device is provided to avoid an interconnection delay of a cell plate by forming a low-resistive conductive layer on a capacitive upper electrode. An insulation layer having a first concave part(15a) is formed on a semiconductor substrate(10). A plurality of capacitive devices include a capacitive lower electrode(16), a capacitive insulation layer(17) and a capacitive upper electrode(18A). The capacitive lower electrode having a second concave part(15b) is formed on the wall and bottom of the first concave part. The capacitive insulation layer having a third concave part(15c) is formed on the wall and bottom of the second concave part. The capacitive upper electrode is formed on the wall and bottom of the third concave part. At least part of the capacitive upper electrode constituting the plurality of capacitive devices is coated with a conductive layer(19A) having lower resistance than the capacitive upper electrode wherein the conductive layer is formed across the plurality of capacitive devices. The capacitive upper electrode is buried in the third concave part. The planar shape of the capacitive upper electrode is almost the same as that of the conductive layer.
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