| 摘要 |
A test mode circuit is provided to adjust a delay time of an input test signal by driving the test mode circuit as a multiplexer, which is arranged in a scan cell unit. An input buffer(361) receives a pin test signals. A scan input unit(371) receives a test control signal and a scan input signal. A delay unit(380) includes plural series-connected cell unit delay members. Plural combination units(362~366) output a signal for regulating the delay time of the delay unit. An output unit(385) receives signals from the delay unit and the combination unit. Plural selectors(310,320,330,340,350) receive a test signal and control the combination unit. During a scan mode, the selectors and the combination units are disabled, the delay unit is enabled, and the scan input signal is delivered to the output units via the delay unit. During a normal mode, the selectors are alternately enabled, the combination units are alternately selected according to a control signal from the enabled selector. Then, the pin test signal is delivered to a corresponding cell unit delay units via the selected combination unit.
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