发明名称 ELECTRODE STRUCTURE OF WIRING SUBSTRATE OF SEMICONDUCTOR DEVICE HAVING EXPANDED PITCH
摘要 AN ELECTRODE STRUCTURE AS WELL AS THE FABRICATION METHOD THEREOF IS DISCLOSED WHICH MAY ENABLE SUCCESSFUL PAD LAYOUT CONVERSION OF INTERCONNECTION ELECTRODE PADS (7) ON THE PERIPHERY OF AN ASSOCIATED IC CHIP (1) TO A GRID ARRAY ROWS AND COLUMNS OF TERMINAL SOLDER PADS (4) ARRANGED OCCUPYING THE ENTIRE AREA OF THE OPPOSITE SURFACE OF THE CHIP (1) WHILE PERMITTING USE OF A MINIMIZED LENGTH OF WIRE LEADS FOR INTERCONNECTION THEREBETWEEN. ‘THIS IS ACHIEVED BY CI) PREPARING A FLAT SQUARE IC CHIP (1) WHICH HAS AN ARRAY OF REGULARLY SPACED PERIPHERAL BONDING PADS (7) THE NUMBER OF WHICH ALONG EACH OF FOUR CHIP SIDES IS EQUALLY DEFINED A FUNCTION OF 2I(2I-L) WHERE “I” IS AN INTEGER AND WHICH ALSO HAS EXTERNAL CONNECTION PADS MADE OF ALUMINUM, (II) SEQUENTIALLY FORMING NICKEL AND GOLD COAT FILMS ON THE CHIP (1) BY ELECTROLESS PLATING TECHNIQUES, (III) ELECTRICALLY COUPLING BY METAL CONTACTS USING THERMAL COMPRESSION-. BONDING TECHNIQUES THE PERIPHERAL BONDING PADS (7) TO THE PAD LAYOUT CONVERSION SUBSTRATE FOR REARRANGEMENT OF THE PERIPHERAL BONDING PADS (7) INTO THE GRID ARRAY OF SOLDER PADS (4), AND (IV) FILLING AN ADHESION RESIN BETWEEN THE CONVERSION SUBSTRATE(2) AND THE IC CHIP (1) (FIGURES 1 AND 7)
申请公布号 MY127710(A) 申请公布日期 2006.12.29
申请号 MY1997PI00151 申请日期 1997.01.16
申请人 HITACHI LIMITED 发明人 MAMORU MITA;MASAKAZU ISHINO;RYOHEI SATOH
分类号 H01L21/60;H01L23/48;H01L23/12;H01L23/31;H01L23/498;H01L23/52;H01L29/40 主分类号 H01L21/60
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