MEMORY DATA ACCESS SCHEME

摘要

A bitline selection network (300; 500) is composed of a plurality of bitlines (BLn7, ..., BLOO) and one or more global bitlines (GBL7, ..., GBLO; GBL) . The bitlines are grouped into bytes (BYTEn, ..., BYTEO) with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor (BLSTn7, ..., BLSTOO) . Each of the bitline select transistors is activated (BLSn7, ..., BLSOO) one at a time by a bitline select controller (350) . Global bitlines may be connected through bit select transistors (BST7, ..., BSTO) and activated one at a time by a bit select controller (385) to a source line (388; 588) , which in turn connects to a sense amplifier (395) and a write data loading logic block (390) . The sense amplifier and the write data loading logic block are used in read and write operations respectively.