发明名称 Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design
摘要 A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; calculating a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided; and calculating a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided.
申请公布号 US2006294482(A1) 申请公布日期 2006.12.28
申请号 US20050165778 申请日期 2005.06.24
申请人 LSI LOGIC CORPORATION 发明人 TETELBAUM ALEXANDER
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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