发明名称 FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a field effect transistor which can reduce GIDL (Gate-Induced Drain Leakage), while suppressing the degradation of ON-current. SOLUTION: The field effect transistor comprises a semiconductor layer, projecting from a base plane to the upper part, a gate electrode formed on the both sides of this semiconductor layer, a gate insulating film which is interposed between this gate electrode and the sides of the semiconductor layer, a source/drain region where a first electric conduction type impurities are implanted into the semiconductor layer, and a channel forming region, put in between the above source/drain regions of the semiconductor layer. The field effect transistor has regions where the first conductivity-type impurities with the concentration gradient of the direction of the channel length which is more gradual than the concentration gradient of the direction of channel length of the first conductivity-type impurities, in a part for the lower part, are implanted into the semiconductor layer upper part in source/drain region. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006351781(A) 申请公布日期 2006.12.28
申请号 JP20050175268 申请日期 2005.06.15
申请人 NEC CORP 发明人 TANAKA KATSUHIKO;TAKEUCHI KIYOSHI
分类号 H01L29/786 主分类号 H01L29/786
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