发明名称 Decision feedback equalizer
摘要 In some embodiments, a circuit is provided that comprises a decision feedback equalizer to receive a bit stream signal. The equalizer comprises a summing circuit having a first input to receive a cursor bit sample from the bit stream, a second input to receive a first cursor bit signal, and an output to provide a cursor bit output signal corresponding to the cursor bit sample with at least some postcursor distortion removed therefrom. Other embodiments are disclosed and/or claimed herein.
申请公布号 US2006291552(A1) 申请公布日期 2006.12.28
申请号 US20050159522 申请日期 2005.06.22
申请人 YEUNG EVELINA F;DABRAL SANJAY;JAUSSI JAMES E;TRIPATHI ALOK 发明人 YEUNG EVELINA F.;DABRAL SANJAY;JAUSSI JAMES E.;TRIPATHI ALOK
分类号 H03H7/30;H04B1/10 主分类号 H03H7/30
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