发明名称 MEMORY CELL ARRAY AND FORMING METHOD THEREOF
摘要 <P>PROBLEM TO BE SOLVED: To provide an improved memory cell array comprising a trench capacitor, and an improved method to form it. <P>SOLUTION: A gate electrode 85 is provided during formation of a transistor, which is performed after an element separation trench 2 and an corresponding active region are formed. That process includes a process to etch an insulating material which adjoins a channel in the element separation trench 2, preventing a part of the channel from being covered. A channel part 11 is ridge-shaped to comprise one top surface 11a and two side surfaces 11b. There are further provided a process for providing a gate insulating layer 84 to the channel part 11, and a process for providing a conductive material 85 on the gate insulating layer 84. The process of etching the insulating material in the element separation trench 2 is so performed as the insulating material is locally etched. The insulating material at the upper part of an insulating groove which separates the active regions from each other is held. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006352107(A) 申请公布日期 2006.12.28
申请号 JP20060147601 申请日期 2006.05.29
申请人 INFINEON TECHNOLOGIES AG 发明人 WEIS ROLF
分类号 H01L21/8242;H01L27/108 主分类号 H01L21/8242
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