| 摘要 |
An integrated circuit ( 203 ) for use in processing streams of data generally and streams of packets in particular. The integrated circuit ( 203 ) includes a number of packet processors ( 307, 313, 303 ), a table look up engine ( 301 ), a queue management engine ( 305 ) and a buffer management engine ( 315 ). The packet processors ( 307, 313, 303 ) include a receive processor ( 421 ), a transmit processor ( 427 ) and a risc core processor ( 401 ), all of which are programmable. The receive processor ( 421 ) and the core processor ( 401 ) cooperate to receive and route packets being received and the core processor ( 401 ) and the transmit processor ( 427 ) cooperate to transmit packets. Routing is done by using information from the table look up engine ( 301 ) to determine a queue ( 215 ) in the queue management engine ( 305 ) which is to receive a descriptor ( 217 ) describing the received packet's payload.
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