Non-volatile semiconductor memory device layout, has bit lines connected to related isolation devices and extending in direction opposite to connection nodes, where one node is connected to page buffer that is in lower position

摘要

The layout has two layout groups (LAY1, LAY2) arranged adjacent to each other in a lateral direction, where each layout group has a set of page buffers (PB1 - PB8). A set of isolation devices (DTo1 - DTo8) is arranged above the buffers. A set of connection nodes (NCN1 - NCN8) connects the page buffers and corresponding isolation devices. A set of bit lines (BLo1 - BLo8) is connected to respective isolation devices, and extends in a direction opposite to the connection nodes. One of the connection nodes is connected to a page buffer located in a lower position. An independent claim is also included for an integrated circuit memory device comprising a memory cell array.