| 摘要 |
Parallel data path architecture is provided to improve data read/write speed by enabling plural read data paths to couple memory arrays to output data pads of a memory device. A memory array(12) includes plural memory cells, which are configured to store data. Plural data pads(14) are configured to supply the data, which is retrieved from the memory array during a read process, as an output of a memory device. Parallel read data paths are coupled between the memory array and the data pads, and each includes plural asynchronous and synchronous data paths(16,18), which operate in different operation modes. A mode selector(22) is configured to select one of the parallel read data paths, so that the data from the memory array is supplied to the data pads.
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