发明名称 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To prevent generation of defective leak due to breakdown through an upper electrode and a capacitance dielectric film because of difference in contact depth at the upper and lower electrodes during the etching process of via holes in an MIM type capacitance element. SOLUTION: The MIM type capacitance element is formed by forming the lower electrode 12a and the upper electrode leadout layer 12b in the same wiring layer on the substrate, forming a capacitance insulating film 13 only on the lower electrode 12a, forming the upper electrode 14 covering the upper electrode leadout layer 12b from the capacitance insulating film 13, and electrically connecting the upper electrode 14 and the upper electrode leadout layer 12b. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006351748(A) 申请公布日期 2006.12.28
申请号 JP20050174610 申请日期 2005.06.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KURIMOTO YUICHI;TANAKA MITSUO
分类号 H01L21/822;H01L21/3205;H01L23/52;H01L27/04 主分类号 H01L21/822
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