| 摘要 |
<p>A cell array of a NAND flash memory device is provided to prevent a lowering effect at the operating speed of a program by minimizing parasitic capacitance between a source select transistor and a flash memory cell. An isolation layer(402) is formed in a predetermined interval on an isolation region of a semiconductor substrate. A source select line(SSL), a plurality of word lines(WL0-WLn), and a drain select line(DSL) are formed vertically to the isolation layer. A junction region(401) is formed on an active region between the word lines. A common source(403) is formed on the active region between the source select lines. A drain(404) is formed on the active region between the drain select lines. One sidewall of the source select line is formed with a shape of sawtooth. A gap between the select line and the word lines on the isolation layer is wider than a gap between the select line and the word lines on the junction region.</p> |
