发明名称 |
Versatile feedback system for phase locked loop architecture |
摘要 |
A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.
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申请公布号 |
US7154344(B2) |
申请公布日期 |
2006.12.26 |
申请号 |
US20040016690 |
申请日期 |
2004.12.17 |
申请人 |
STMICROELECTRONICS LIMITED |
发明人 |
THIES WILLIAM;LAWLEY CHRIS |
分类号 |
H03L7/10;H03L7/00;H03L7/18;H03L7/197 |
主分类号 |
H03L7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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