PLL circuit having reduced capacitor size

摘要

A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where $V_{\mathrm{VCO}}=\frac{x}{C^{\text{'}}}{I}_{\mathrm{CP2}}t+I_{\mathrm{CP2}}\mathrm{R2}$ V_VCO=VCO input voltage I_cp2 is the current output by the second charge pump R₂=second resistance C'=new capacitance value=C*X C=original capacitance value.