| 摘要 |
A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit generates a second blanking signal, which has a duration corresponding with the duration of the noise introduced to the read count value, in response to the second clock signal. The read and write count values are latched into read and write blanking registers, respectively, in response to the first and second blanking signals, respectively, effectively filtering the introduced noise prior to a subsequently performed comparison operation.
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