发明名称 |
Clock controller for at-speed testing of scan circuits |
摘要 |
A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
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申请公布号 |
US7155651(B2) |
申请公布日期 |
2006.12.26 |
申请号 |
US20040013319 |
申请日期 |
2004.12.17 |
申请人 |
LOGICVISION, INC. |
发明人 |
NADEAU-DOSTIE BENOIT;COTE JEAN-FRANCOIS |
分类号 |
G01R31/28;G01R31/3185;G01R31/319 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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