| 摘要 |
N shared data registers are provided for N+1 processors, respectively. For allowing all the processors to read the same data from the shared data registers, the processors are connected by interprocessor communication channels. The processors are classified into a master processor and subordinate processors. All data writing into the shared data registers are executed from the master processor. Further, data writing into the shared data registers from the subordinate processor is executed from the master processor after a write request is sent to the master processor.
|
