| 摘要 |
A clock signal is generated by receiving an input clock signal having an input clock signal frequency, dividing the input clock signal frequency by a selected number to produce a lower frequency output clock signal, and shifting the phase of the output clock signal. The phase can be shifted by changing, for at least a predetermined amount of time, the selected number by which the input clock signal frequency is divided, and then restoring the selected number to its original value. The clock can be used as a channel sampling clock, and it can be synchronized to the data by the phase shifting. One implementation uses a chain of flip-flops for dividing the frequency and additional circuitry for shifting phase. The flip-flops may be connected with minimum logic in order to operate at substantially the highest frequency reachable by a given transistor technology.
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