发明名称 Dummy fill for integrated circuits
摘要 A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
申请公布号 US7152215(B2) 申请公布日期 2006.12.19
申请号 US20020164847 申请日期 2002.06.07
申请人 PRAESAGUS, INC. 发明人 SMITH TABER H.;MEHROTRA VIKAS;WHITE DAVID
分类号 G06F17/50;H01L21/3105;H01L21/321;H01L21/768;H01L23/522;H01L27/02 主分类号 G06F17/50
代理机构 代理人
主权项
地址