| 摘要 |
The present invention avoids generation of voids in regions in which bit line contacts CB are to be formed in a row. A semiconductor memory, mounted on a semiconductor chip, includes bit lines BL and a source line SL and word lines WL orthogonal to the bit lines. The device further includes: bit line side select gate lines SGD and source line side select gate lines SGS that are aligned parallel to the word lines and adjacent to both ends thereof aligned along the bit line length; memory cell transistors MT that are arranged at the intersections of the bit lines and the word lines; select gate transistors ST that are arranged at the intersections of the bit lines and the select gate lines; bit line contacts CB that are arranged along the word line length between the bit line side select gate lines; and source line contacts CS that are arranged along the word line length between the source line side select gate lines; wherein interval L 1 between the bit line side select gate lines is greater than interval L 2 between the source line side select gate lines.
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