| 摘要 |
A bus matrix structure for reducing latency time is provided to reduce the latency time by removing an input stage, and remove latency of one clock cycle, and reduce hardware overhead and a clock cycle of a bus matrix by improving a structure of a decoder, an output stage, and an arbiter. Each decoder(110) is directly connected to a master layer, and includes one flip-flop and two multiplexers. Each output stage(120) includes the arbiter(130) selecting a master by using a round robin mode, corresponds to each decoder, and is connected to each slaver layer. The flip-flop determines a data section. Each multiplexer outputs a response signal of the output stage without any change if a master selection signal of the output stage is '1' and generates a delayed response if the master selection signal is '0'.
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