| 摘要 |
A method for forming a floating gate array of a flash memory device is provided to enhance the degree of integration by minimizing the distance between floating gates regardless of the minimum CD(Critical Dimension) of design rule. A tunnel oxide layer(12), a floating gate forming layer, a capping oxide layer(16) and a first nitride pattern are sequentially formed on a semiconductor substrate(10). A first oxide spacer is formed at both sidewalls of the first nitride pattern. The first nitride layer pattern is removed therefrom. A plurality of second nitride patterns(22) are formed on the capping layer, wherein the second nitride patterns are spaced apart from each other due to the first oxide spacer. The floating gate forming layer is selectively exposed to the outside by removing the first oxide spacer and the capping oxide layer therefrom. A plurality of floating gate patterns(14) are formed on the resultant structure by removing selectively the floating gate forming layer using the second nitride patterns as an etch mask. A sidewall oxide layer(14c) is formed at a predetermined portion between adjacent floating gates by oxidizing each sidewall of the floating gate.
|
