| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a data processor capable of executing processing speedily while suppressing a consumption current when writing long data to a storage. <P>SOLUTION: A cache control section 31 holds an address and long data output from a CPU 1 in a cycle of a write request of 32-bit long data from the CPU 1, stores only 8 bits in the 32-bit long data to be written at the storage region of an MRAM 32 corresponding to an address output from the CPU 1, and stores remaining data that are not stored in the MRAM 32 in the held long data at the storage region of the MRAM 32 corresponding to the held address in 8-bit units in a cycle when the CPU 1 does not request the read/write of data to the MRAM 32. <P>COPYRIGHT: (C)2007,JPO&INPIT |
