| 摘要 |
PROBLEM TO BE SOLVED: To provide a wafer of a large-scale integrated circuit improved in such a way that a semiconductor device can be estimated in a short time with ease without increasing the width of a scribed line. SOLUTION: A plurality of semiconductor devices 1 are arranged in a direction where a first scribed line 12a extends to form a train of the semiconductor devices. A plurality of the trains of the semiconductor devices are provided in a direction where a second scribed line 12b extends perpendicularly to the first scribed line 12a. A relay circuit 9 is provided in the second scribed line 12b so as to be paired with each semiconductor device 1. The relay circuit 9 and the semiconductor device 1 are connected with each other through polysilicon wiring 13. Second layer wiring 6 connected, at its one end, with the relay circuit 9 extends in the second scribed line 12b. Third layer wiring 5c connected at its one end with a pad electrode 4a formed in a test chip 3 extends in the first scribed line 12a. The second layer wiring 6 and the third layer wiring 5a are electrically connected with each other through a via hole 10. COPYRIGHT: (C)2007,JPO&INPIT
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