| 摘要 |
An (N-1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N-1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N-1)/N prescaler receives a divide-by-(N-1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N-1); otherwise, the prescaler divides by a factor of N.
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