发明名称 DERIVING FRACTIONAL CLOCK PERIOD ERROR INFORMATION
摘要 <p><P>PROBLEM TO BE SOLVED: To increase accuracy in local clock synchronization without increasing local clock frequency. <P>SOLUTION: The present invention relates to techniques for determining a synchronization error of a local clock (52) by deriving fractional clock period error information. A system for determining a synchronization error according to the present techniques generates a timing message in response to a master clock (30) and includes an error measurement circuit (72) that determines a synchronization error for a local clock in response to the timing message such that the synchronization error includes a fraction of a period of the local clock. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006340366(A) 申请公布日期 2006.12.14
申请号 JP20060153361 申请日期 2006.06.01
申请人 AGILENT TECHNOL INC 发明人 CORREDOURA PAUL L
分类号 H04L7/00;G04G7/00 主分类号 H04L7/00
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