CIRCUIT SPLITTING IN ANALYSIS OF CIRCUITS AT TRANSISTOR LEVEL
摘要
<p>Analyzing the integrated circuit using node model and dividing the node edges to form two sub graphs that represent two sub circuits of the integrated circuit with operating splitting method figure 3 for splitting and analyzing the two sub circuits for improved computation efficiency and improved processing speed.</p>
申请公布号
WO2006132639(A1)
申请公布日期
2006.12.14
申请号
WO2005US20242
申请日期
2005.06.07
申请人
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA;CHENG, CHUNG-KUAN;ZHU, ZHENGYONG;SHI, RUI
