发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To enable surely read-out even when storage node voltage is reduced. <P>SOLUTION: The apparatus has a variable capacitance capacitor C for each memory cell 1A. One electrode of the variable capacitance capacitor C is connected to a storage node SN, and the other electrode is connected to a control line ( read-out word line RWL) to which high level voltage is applied at the time of data output. A capacity value of the variable capacitance capacitor C is varied in accordance with a voltage level of the storage node SN at the time of data holding, and voltage of the storage node is boosted by applying high level voltage from the read-out word line RWL. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006338729(A) 申请公布日期 2006.12.14
申请号 JP20050159712 申请日期 2005.05.31
申请人 SONY CORP 发明人 OTSUKA WATARU
分类号 G11C11/405;H01L21/8242;H01L27/108 主分类号 G11C11/405
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