| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a PLL circuit with a phase delay circuit that defines a delay signal value so as to correctly sample a video signal at all times. <P>SOLUTION: In the PLL circuit wherein a DFF 3 applies 1/2 frequency division to a [VCO] signal output from a VCO 15 of the PLL circuit to generate a clock in compliance with the VESA standard, a DFF 4 applies 1/2 frequency division to a [VCO_Delay] signal to which an arbitrary phase delay is given by a phase delay control circuit 2 to produce a [1/2 Div_Delay] signal used for sampling the video signal by an A/D converter, an OR circuit 9 detects phases of the [VCO] signal and the [1/2 Div_Delay] signal, when the phase of the [VCO] signal is inverted to the phase of the [1/2 Div_Delay] signal, a DFF 6 outputs [Reset] signal to reset the DFF 3 and the DFF 4. <P>COPYRIGHT: (C)2007,JPO&INPIT |
