发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PRODUCTION PROGRAM OF LAYOUT PATTERN
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which whether a design layout pattern is good or not can be discriminated and a clear guideline for correction is presented. <P>SOLUTION: A tendency of inducing wiring failures in a design layout pattern of a semiconductor device by lithography and processing is quantified as a score; whether the design layout pattern is good or not is discriminated by the score; and if the pattern is discriminated as good, a transfer layout pattern transferred from the design layout pattern is formed on a semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006337668(A) 申请公布日期 2006.12.14
申请号 JP20050161539 申请日期 2005.06.01
申请人 TOSHIBA CORP 发明人 URAKAWA YUKIHIRO
分类号 G03F1/68;G03F1/70;H01L21/82 主分类号 G03F1/68
代理机构 代理人
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