发明名称 |
Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device |
摘要 |
A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer may be formed to electrically short the upper and lower portions of the sidewall and eliminate the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and structures are described.
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申请公布号 |
US2006281319(A1) |
申请公布日期 |
2006.12.14 |
申请号 |
US20060506297 |
申请日期 |
2006.08.18 |
申请人 |
HOWARD BRADLEY J;CHOPRA DINESH |
发明人 |
HOWARD BRADLEY J.;CHOPRA DINESH |
分类号 |
H01L21/311;H01L21/033;H01L21/302;H01L21/461;H01L21/768;H01L21/8242;H01L29/00 |
主分类号 |
H01L21/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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