| 摘要 |
A synchronous semiconductor memory device is provided to detect a write recovery time(tWR) error even when a probe test is performed at a lower frequency than the specification. A logic assembly part(10) generates a set signal and a reset signal, by assembling an active command signal, a test mode signal, a clock enable signal and an internal precharge flag signal. An SR-latch part(20) receives the set signal and the reset signal. A pulse width control part(30) outputs a word line driving control signal by controlling the pulse width of an output signal of the SR-latch part.
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